Architecture-aware low-density parity-check codes

A high-throughput memory-efficient decoder architecture for archit~ E ~ U ~ O B W B I ~ low-density parity-check (LDPC) codes is proposed based on a novel turbo-decoding algorithm. The aichltecture benefits from various optimizations at the code-design, decoding algorithm, and decoder architecture levels. The interconnect complexity and memory overhead problems of current decoder implementations are reduced by designing slructured or erehiteeture-aware LDPC codes and employing a new turbo-decoding algorithm. An efficient memory architecture coupled with a scalable and dynamic transport network for storing and routing messages are proposed. Simulations demonstrate that the proposed architecture attains a throughput of 1.92Gbits/s for a frame length of 2304 bits, and achieves saving of 89.13% and 62.80% in power consumption and silicon area over state-of-the-art. with B reduction of 60.5 % in interconnect Wires.